Semiconductor device and manufacturing method thereof

ABSTRACT

A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor device andmethod of manufacturing the semiconductor device and, more particularly,technique reducing contact resistance at contacting upper layer andlower layer. Further the invention relates to forming a bump electrode.

[0002] Explanation is made below on the conventional semiconductordevice and method of manufacturing the semiconductor device, withreference to the drawings.

[0003] In FIG. 14, numeral 1 denotes a semiconductor substrate, on whicha gate electrode 3 is formed through gate oxide film 2, and source/drainregions 4 are formed so as to be adjacent to the gate electrode 3. Ainterlayer insulating film 5 covering the gate electrode 3 is formed,and source/drain electrodes 7 contacting the source/drain regions 4through contact holes 6 formed at the interlayer insulating film 5 areformed.

[0004] In FIG. 15 and FIG. 16, numeral 11 denotes a semiconductorsubstrate, on which an insulating film 12 including LOCOS oxide film isformed, and a lower layer wiring 13 is formed on the insulating film 12.

[0005] An interlayer insulating film 14 is formed so as to cover thelower layer wiring 13, and an upper layer wiring 16 is formed so as tocontact the lower wiring 13 through via holes 15 formed at theinterlayer insulating film 14.

[0006] A passivation film 17 is formed so as to cover the upper layerwiring 16, and a gold bump electrode 18 is formed at a pad portion 17Awhere the passivation film 17 is opened.

[0007] Here, in the semiconductor device shown in FIG. 14, step coverageof metal film in a contact hole decreases in accordance with thereduction of the contact hole when metal film such as Al and the like isdeposited by spattering method at forming the source/drain electrode.Because of that, a device is made practicable nowadays, wherein filmsuch as tungsten film and the like having conductivity in the contacthole is buried by CVD method and, on the film, metal film such as Aletc. is formed for metal wiring layer by patterning.

[0008] In the case of constitution of various kinds of transistorsadopting such the plug contact technique, when sizes of contact holesare various, recess depth at etch back after burying become various, andto say extremely, the recess values possibly become worse to similardegree as the case without burring step coverage of metal film.

[0009] Because of that, in the case of constitution of various kinds oftransistors by michronization process such as 0.35 μm, it is need tomake each size of contact hole even to the size of contact hole of thetransistor in the minimum design rule, and contact resistance becomeshigh in some transistor so that there is a problem of rise ofon-resistance.

[0010] In the semiconductor device shown in FIG. 15 and FIG. 16, whenthere are the via holes 15 under the above-mentioned pad portion,difference in surface of the via holes remains even on surface of thegold bump electrode 18. Because of that, difference in surface of thegold bump electrode 18 causes decrease of yield at mounting on mountingpoints of TAB (Tape Automated Bonding) and the like for example.

[0011] Especially, in the case of constitution of various kinds oftransistors by michronization process such as 0.35 μm, opening diameterof the pad portion is constituted by plural micro via holes because theminimum dimension is applied for dimension of each via hole (contacthole). Because of that, difference in surface remains like surface ofthe above-mentioned gold bump electrode 18.

SUMMARY OF THE INVENTION

[0012] According to the present invention, a semiconductor device and amethod of manufacturing the semiconductor device of the invention havinga transistor on a semiconductor substrate include contact portions forconnecting a lower layer and an upper layer with contact arranged inplural lines.

[0013] A semiconductor device and a method of manufacturing thesemiconductor device of the invention having a first transistor and asecond transistor on a semiconductor substrate includes numbers offorming contact portions for connecting a lower layer and an upper layerwith contact are different at the first transistor and the secondtransistor.

[0014] A semiconductor device and a method of manufacturing thesemiconductor device of the invention include contact portions forconnecting the lower layer and the upper layer with contact arranged inone line in the first transistor, and contact portions for connectingthe lower layer and the upper layer with contact arranged in plurallines in the second transistor.

[0015] A semiconductor device and a method of manufacturing thesemiconductor device of the invention include the second transistorhaving a source/drain region so as to be adjacent to a gate electrode,and a semiconductor region constituting a channel is formed under thegate electrode.

[0016] A semiconductor device and a method of manufacturing thesemiconductor device of the invention include a low concentration regionof the same conductive type formed so as to connect to the source/drainregion and to contact the semiconductor region under the gate electrodeof the second transistor.

[0017] A semiconductor device and a method of manufacturing thesemiconductor device of the invention include a low concentration regionof the same conductive type being extended shallowly to thesemiconductor so as to connect to the source/drain region and to contactthe semiconductor region under the gate electrode of the secondtransistor.

[0018] According to a semiconductor device and a method of manufacturingthe semiconductor device of the invention, the contact portions areprovided for connecting to the source/drain region with contact.

[0019] According to a semiconductor device and a method of manufacturingthe semiconductor device of the invention, the contact portions areprovided for connecting to the lower layer wiring and upper layer wiringwith contact.

[0020] A semiconductor device and a method of manufacturing thesemiconductor device of the invention include a film having conductivityburied in the contact portion.

[0021] Further, a semiconductor device including an upper layer wiringconnected to the lower layer wiring with contact through a via holeformed under a bump electrode covering lower layer wiring and method ofmanufacturing the semiconductor device of the invention have the viahole formed at region except under a bump electrode constituted at a padportion.

[0022] Preferably, in the semiconductor device and method ofmanufacturing the semiconductor device, the lower layer wiring isarranged under the bump electrode.

[0023] A method of manufacturing the device includes the steps of:forming in the interlayer insulating film so as to cover the lower layerwiring; forming the upper layer wiring so as to contact the lower layerwiring through the via hole after forming the via hole at region excepta pad forming portion of the interlayer insulating film; and forming abump electrode at a pad portion.

[0024] Thus, smooth of surface of the bump electrode is designed becausethe via hole is not formed under the bump electrode constituted at thepad portion.

[0025] Further, smooth at periphery of the pad portion is not damaged byarranging the lower layer wiring even under the bump electrode.

[0026] A semiconductor device of the invention includes: a gateelectrode formed on a semiconductor substrate through gate oxide film; asource/drain region formed so as to be adjacent to the gate electrode; asemiconductor region formed under the gate electrode and constituting achannel; a lower layer wiring connected to the source/drain region withcontact; a via hole formed in the interlayer insulating film coveringthe lower layer wiring and formed at region except a bump electrodeconstituted at a pad portion; and an upper layer wiring connected to thelower layer wiring with contact through the via hole.

[0027] A method of manufacturing the device including the steps of:forming a low concentration opposite conductive type source/drain regionby ion-implanting opposite conductive type impurity in one conductivetype semiconductor; forming a low concentration opposite conductive typeregion connecting to the low concentration opposite conductive typesource/drain region by ion-implanting opposite conductive type impurity;forming a high concentration opposite conductive type source/drainregion in the low concentration opposite conductive type source/drainregion by ion-implanting opposite conductive type impurity; forming aone conductive type body region dividing the opposite conductive typeregion under the gate electrode by ion-implanting one conductive typeimpurity; forming a lower layer wiring connecting to the source/drainregion with contact through interlayer insulating film covering the gateelectrode; forming a via hole at region except a bump electrodeconstituted at a pad portion of the interlayer insulating film afterforming the interlayer insulating film so as to cover the lower layerwiring; and forming an upper layer wiring connecting to the lower layerwiring with contact through the via hole.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIGS. 1A and 1B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0029]FIGS. 2A and 2B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0030]FIGS. 3A and 3B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0031]FIGS. 4A and 4B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0032]FIGS. 5A and 5B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0033]FIGS. 6A and 6B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0034]FIGS. 7A and 7B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0035]FIGS. 8A and 8B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0036]FIGS. 9A and 9B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0037]FIGS. 10A and 10B are sectional views showing a method ofmanufacturing a semiconductor device of the present invention;

[0038]FIG. 11 is a sectional view showing a method of manufacturing asemiconductor device of a first embodiment of the invention;

[0039]FIG. 12 is a plane view showing a method of manufacturing asemiconductor device of the first embodiment of the invention;

[0040]FIG. 13 is a sectional view showing a method of manufacturing asemiconductor device of a second embodiment of the invention;

[0041]FIG. 14 is a sectional view showing the conventional method ofmanufacturing the semiconductor;

[0042]FIG. 15 is a sectional view showing the conventional method ofmanufacturing the semiconductor; and

[0043]FIG. 16 is a plane view showing the conventional method ofmanufacturing the semiconductor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0044] With reference to the drawings, explanation will be now made on asemiconductor device and method of manufacturing the semiconductordevice of the present invention in the case applied to the semiconductordevice mounted with of various kinds of MOS transistors constitutingvarious kinds of display drivers such as liquid crystal driver and EL(electroluminescence) driver.

[0045] The display driver is configured with, as viewed from the left inFIG. 10A, logic N-channel MOS and P-channel MOS transistors (e.g. on 3V), an N-channel MOS transistor (e.g. on 30 V) for a level shifter andan N-channel high-voltage MOS transistor of high withstand voltage (e.g.on 30 V) and, as viewed from the left in FIG. 10B, an N-channelhigh-voltage MOS transistor of high withstand voltage (e.g. on 30 V)reduced in on-resistance, a P-channel high-voltage MOS transistor ofhigh withstand voltage(e.g. on 30 V) and a P-channel high-voltage MOStransistor of high withstand voltage (e.g. on 30 V) reduced inon-resistance. Note that, in the below explanation, the MOS high-voltagetransistor reduced in on-resistance is referred to as an SLED (Slitchannel by counter doping with extended shallow drain) MOS transistor inorder to differentiate between the high-voltage MOS transistor and thehigh-voltage MOS transistor reduced in on-voltage, for the sake ofexplanation.

[0046] In the semiconductor device mounted with various MOS transistorsconstituting such a display driver, as shown in FIGS. 10A and 10B, an Ntype well region 23 forming the P-channel high-voltage transistor andthe P-channel high-voltage SLEDMOS transistor reduced in on-resistanceis configured in a step higher region, while a P type well region 22forming the other MOS transistors is configured in a step lower region.In other words, structuring is made to arrange the precise logic (e.g.3V) N-channel MOS and P-channel MOS transistors in the step lowerregion.

[0047] Explanation is made below on a method of manufacturing asemiconductor device mounted with various transistors constituting thedisplay driver described above.

[0048] In FIGS. 1A and 1B, in order to define a region for formingvarious MOS transistors, a P type well (PW) 22 and an N type well (NW)23 are first formed using LOCOS technique, e.g. in a p typesemiconductor substrate (P-sub).

[0049] That is, although explanation with showing is omitted, a padoxide film and a silicon nitride film are formed on the well region ofthe semiconductor substrate 21. The pad oxide film and silicon nitridefilm is used as a mask to ion-implant boron ion, for example, at anacceleration voltage of approximately 80 keV and a dose of 8×10¹²/cm²,thereby forming an ion-implant region. Thereafter, the silicon nitridefilm is used as a mask to oxidize the substrate surface by the LOCOStechnique, thereby forming a LOCOS film. At this time, the boron ionimplanted in a region beneath the LOCOS film is diffused toward theinward of the substrate to form a P type region.

[0050] Next, the pad oxide film and the silicon nitride film areremoved. Thereafter, the LOCOS film is used as a mask to ion-implantphosphorus ion to the substrate surface, at an acceleration voltage ofapproximately 80 keV and a dose of 9×10¹²/cm², thereby forming anion-implant region 15. Then, the LOCOS film is removed away. Thereafter,the impurity ions implanted in the substrate are thermally diffused toform a P type well and N type well. Thus, as shown in FIGS. 1A and 1B,the P type well 22 formed in the substrate 21 is arranged in a steplower region while the N type well is arranged in a step higher region.

[0051] Next, in FIGS. 2A and 2B, a device isolation film 24 is formed toan approximately 500 nm by the LOCOS process in order for deviceisolation based on the MOS transistor. A thick gate oxide film 25 forwithstanding high voltage is formed by thermal oxidation in a thicknessof approximately 80 nm on an active region excepting the deviceisolation region.

[0052] Subsequently, the resist film is used as a mask to form firstlow-concentration N type and P type source/drain regions (hereinafter,referred to as LN region 26, LP region 27). Namely, in a state coveringthe region of other than an LN region by a not-shown resist film,phosphorus ion, for example, is first ion-implanted to the substratesurface layer at an acceleration voltage of 120 keV and a dose of 8×10¹²/cm² thereby forming an LN region 26. Thereafter, in a statecovering the region of other than an LP region by a resist film (PR),boron ion, for example, is ion-implanted to the substrate surface layerat an acceleration voltage of 120 keV and a dose of 8.5×10¹²/cm² therebyforming an LP region 27. Note that, in actual, the implanted ionicspecies will be thermally diffused into a LN region 26 and LP region 27through an anneal process as a later process (e.g. in an N₂ atmosphereat 1100° C. for 2 hours).

[0053] Subsequently, in FIGS. 3A and 3B, using as a mask a resist filmat between the LN regions 26 and the LP regions 27 forming the regionsfor P-channel and N-channel SLEDMOS transistors, secondlow-concentration N type and P type source/drain regions (hereinafter,referred to as SLN region 28 and SLP region 29) are formed. Namely, in astate covering the region other than the region for an SLN region by anot-shown resist mask, phosphorus ion, for example, is firstion-implanted to the substrate surface layer at an acceleration voltageof 120 keV and a dose of 1.5×10¹²/cm² to form an SLN region 28continuing the LN regions 26. Then, in a state covering the other regionof the SLP region by a resist film (PR), boron difluoride (⁴⁹BF₂ ⁺), forexample, is ion-implanted to the substrate surface region at anacceleration voltage of 140 keV and a dose of 2.5×10¹²/cm² to form anSLP region 29 continuing the LP regions 27. Note that the LN region 26and the SLN region 28 or the LP region 27 and the SLP region 29 are setnearly equal in impurity concentration or higher in either one.

[0054] Furthermore, in FIGS. 4A and 4B, a resist film is used as a maskto form high-concentration N type and P type source/drain regions(hereinafter, referred to as N+ region 30, P+ region 31). Namely, in astate covering the other region than a region for an N+ region by anot-shown resist film, phosphorus ion, for example, is firstion-implanted to the substrate surface layer at an acceleration voltageof 80 keV and a dose of 2×10¹⁵/cm² thereby forming an N+ region 30.Thereafter, in a state covering the other region than a region for a P+region by a resist film (PR), boron difluoride ion, for example, ision-implanted to the substrate surface layer at an acceleration voltageof 140 keV and a dose of 2×10¹⁵/cm² thereby forming a P+ region 31.

[0055] Next, in FIGS. 5A and 5B, using as a mask a resist film having anopening diameter smaller than the mask opening diameter (see FIG. 13)for forming the SLN region 28 and SLP region 29, opposite-conductivitytype impurities are ion-implanted to a central area of the SLN region 28continuing the LN regions 26 and to a central area of the SLP region 29continuing the LP regions 27, thereby forming a P type body region 32and an N type body region 33 to respectively separate the SLN region 28and the SLP region 29. Namely, in a state covering the other region thanthe region for a P type region by a not-shown resist film, borondifluoride ion, for example, is first ion-implanted to the substratesurface layer at an acceleration voltage of 120 keV and a dose of5×10¹²/cm² thereby forming a P type body region 32. Thereafter, in astate covering the other region than the region for an N type region bya resist film (PR), phosphorus ion, for example, is ion-implanted to thesubstrate surface layer at an acceleration voltage of 190 keV and a doseof 5×10¹²/cm² thereby forming an N type body region 33. Note that theoperation processes concerning ion implant shown in FIGS. 3A to 5B maybe properly changed in order. The P type body region 32 and the N typebody region 33 each will be constituted with a channel in a surfaceregion thereof.

[0056] Furthermore, in FIGS. 6A and 6B, a second P type well (SPW) 34and a second N type well (SNW) 35 are formed in the substrate (P typewell 22) at a region for precise N-channel and P-channel MOSnormal-voltage transistors.

[0057] Namely, using a not-shown resist film having an opening in theregion for an N-channel normal-voltage MOS transistor as a mask, boronion, for example, is ion-implanted to the P type well 22 at anacceleration voltage of approximately 190 keV and a dose of (firstimplant condition) 1.5×10¹³/cm². Thereafter, boron ion is againion-implanted at an acceleration voltage of approximately 50 keV and adose of (second implant condition) 2.6×10¹²/cm², thus forming a second Ptype well 34. Also, using a resist film (PR) having an opening in theregion for a P-channel normal-voltage MOS transistor as a mask,phosphorous ion, for example, is ion-implanted to the P type well 22 atan acceleration voltage of approximately 380 keV and a dose of1.5×10¹³/cm², thereby forming a second N type well 35. Note that, wherea high-acceleration voltage generating apparatus having nearly 380 keVis not available, it is satisfactory to use a double charge scheme forion-implant two-valence phosphorus ion at an acceleration voltage ofapproximately 190 keV and a dose of 1.5×10¹³/cm². Subsequently,phosphorus ion is ion-implanted at an acceleration voltage ofapproximately 140 keV and a dose of 4.0×10¹²/cm².

[0058] Next, removed is the oxide film 25 from the regions for N-channeland P-channel normal-voltage MOS transistors and for a level-shifterN-channel MOS transistor. Thereafter, as shown in FIGS. 7A and 7B, agate oxide film having a desired film thickness is newly formed on theabove region.

[0059] Namely, a gate oxide film 36 is formed on the entire surface bythermal oxidation to approximately 14 nm (approximately 7 nm at thisstage, but the film thickness will increase upon forming a gate oxidefilm for normal voltage referred later) for a level-shifter N-channelMOS transistor. Subsequently, after removing the gate oxide film 36 fora level-shifter N-channel MOS transistor formed on the region forN-channel and P-channel normal-voltage MOS transistors, a thin gateoxide film 37 (approximately 7 nm) for normal voltage is formed on thisregion by thermal oxidation.

[0060] Subsequently, in FIGS. 8A and 8B, a polysilicon film havingapproximately 100 nm is formed over the entire surface. The polysiliconfilm is thermally diffused by POCl₃ as a thermal-diffusion source thusbeing made conductive. Thereafter, a tungsten siliside film havingapproximately 100 nm are formed on the polysilicon film, and further anSiO₂ film having approximately 150 nm thereon. Using a not-shown resistfilm, patterning is made to form gate electrodes 38A, 38B, 38C, 38D,38E, 38F, 38G for MOS transistors. Note that the SiO₂ film serves as ahard mask during the patterning.

[0061] Subsequently, in FIGS. 9A and 9B, low-concentration sorce/drainregions are formed for normal-voltage N-channel and P-channel MOStransistors.

[0062] Namely, using as a mask a not-shown resist film covering theother region than the region for low-concentration source/drain regionsfor a normal-voltage N-channel MOS transistor, phosphorus ion, forexample, is ion-implanted at an acceleration voltage of approximately 20keV and a dose of 6.2×10¹³/cm² to form low-concentration N− typesource/drain regions 39. Meanwhile, using as a mask a resist film (PR)covering the other region than the region for a low-concentrationsource/drain region for a normal-voltage P-channel MOS transistor, borondifluoride ion, for example, is ion-implanted at an acceleration voltageof approximately 20 keV and a dose of 2×10¹³ /cm² to formlow-concentration P-type source/drain regions 40.

[0063] Furthermore, as shown in FIGS. 10A and 10B, a TEOS film 41 havingapproximately 250 nm is formed over the entire surface by the LPCVDprocess in a manner covering the gate electrodes 38A, 38B, 38C, 38D,38E, 38F, 38G. The TEOS film 41 is anisotropically etched through a maskof a resist film (PR) having openings in the region for normal-voltageN-channel and P-channel MOS transistors. This forms sidewall spacerfilms 41A on the sidewalls of the gate electrode 38A, 38B, as shown inFIG. 10A. The TEOS film 41 is left, as it is, in the region covered bythe resist film (PR).

[0064] Then, using the gate electrode 38A, sidewall spacer films 41A,gate electrode 38B and sidewall spacer films 41A as a mask,high-concentration source/drain regions are formed for normal-voltageN-channel and P-channel MOS transistors.

[0065] Namely, using a not-shown resist film covering the other regionthan the region of high-concentration source/drain regions for anormal-voltage N-channel MOS transistor as a mask, arsenic ion, forexample, is ion-implanted at an acceleration voltage of approximately100 keV and a dose of 5×10¹⁵/cm² thereby forming high-concentration N+source/drain regions 42. Also, using a not-shown resist film coveringthe other region than the region of high-concentration source/drainregions for a normal-voltage P− channel MOS transistor as a mask, borondifluoride ion, for example, is ion-implanted at an acceleration voltageof approximately 40 keV and a dose of 2×10¹⁵/cm² thereby forminghigh-concentration P+ source/drain regions 43.

[0066] An interlayer insulating film, including TEOS and BPSG films, isformed to approximately 600 nm and, thereafter, a metal interconnectionlayer is formed to have contact to the source/drain regions 30, 31, 42,43. Thus, completed are normal-voltage N-channel and P-channel MOStransistors, a level-shifter N-channel MOS transistor, high-voltageN-channel and P-channel MOS transistors, and high-voltage N-channel andP-channel SLEDMOS transistors reduced in on-resistance, to constitute adisplay driver such as a liquid-crystal display driver and anelectroluminescence driver.

[0067] (Embodiment 1)

[0068] A first embodiment of the invention will be described.

[0069] A feature of the first embodiment of the invention is in thestructure of contact portion for connecting a metal wring layer 48 toeach of the source/drain regions 30, 31, 42, and 43 with contact and theforming method thereof.

[0070] The structure of the contact portion of the invention will beexplained below referring FIG. 11. Although examples of a normal-voltageMOS transistor (A), a high-voltage MOS transistor (B), and an N-channelSLEDMOS transistor (C) are described in FIG. 11, it is similar about thenormal-voltage MOS transistor, the high-voltae MOS transistor, and theP-channel SLEDMOS transistor.

[0071] In the invention, source/drain electrodes are formed by thefollowing the step of: forming contact holes 46 contacting to thesource/drain regions 30 and 42 in interlayer insulating film 45; formingplug contact portions 47 by burying film such as tungsten film and thelike for example having conductivity in the contact holes 46; andforming metal wring layers 48 of Al film and the like on the plugcontact portions 47 as shown in FIG. 11.

[0072] At this time, arrangement of the plug contact portions 47 aredifferent with respect to the transistor of every kind constituting thedisplay driver. In the embodiment, the plug contact portions 47 arearranged in one line at least for the source/drain regions of thenormal-voltage MOS transistor (A), and for the source/drain region 30 ofthe high-voltage MOS transistor (B) and the SLEDMOS transistor (C), theplug contact portions 47 are arranged in plural lines, for example, twolines (See FIG. 12).

[0073] Because of that, in the invention, contact resistance is reducedby increasing number of the plug contact portions 47 so as to reduceon-resistance of the transistor.

[0074] Thus, in the device having various kinds of transistors andforming contact holes with the minimum dimension at the design ruleaccording to the invention, reduction of contact resistance is designedby setting suitable number of contacts and arranging so as to reduceon-resistance of the transistor.

[0075] The film may be buried with polysilicon film and the like notlimiting to the tungsten film, and further conductive film may used aswring without etch-back instead of burying the conductive film in thecontact hole 46 by etch-back.

[0076] Although the plug contact portions 47 are arranged in one linefor the normal-voltage MOS transistor, the plug contact portions 47 maybe arranged in plural lines for the normal-voltage MOS transistor. Byarranging the plug contact portions 47 in plural lines, reliabilityimproves in the normal-voltage MOS transistor arranged near place to apower source pad for example, and constitution arranging the plugcontact portions 47 in one line is enough only for transmitting “H” and“L” signals.

[0077] Further, although the contact portion for connecting to thesource/drain region with contact is described in the embodiment, theinvention is not limited to this, and it is applicable for contactportion connecting lower layer wiring and upper layer wiring.Especially, in the device where high withstand voltage and lowon-resistance are designed such as SLEDMOS transistor, lower resistancecan be realized by applying the invention to the contact portion forconnecting the lower layer wiring and the upper layer wiring withcontact (for example, two layers wiring and three layers wiring becausethe process is three layers wiring structure).

[0078] (Embodiment 2)

[0079] A second embodiment of the present invention will be describedbelow.

[0080] A feature of the second embodiment of the invention is to smooththe surface of the bump electrode by not forming a via hole under thebump electrode constituted at a pad portion in the device where an upperwiring is contacted through the via hole formed at interlayer insulatingfilm covering a lower wiring.

[0081] By forming the lower wiring even under the bump electrode, smoothof periphery of the pat portion is not damaged.

[0082] A structure of a semiconductor of the invention will be describedbelow referring FIG. 13. Although an example applying the invention forN-channel SLEDMOS transistor in FIG. 13 is introduced, other transistorsare formed similarly.

[0083] In FIG. 13, a first layer wiring 57 is formed on a source/drainregion 30 (structure of drain side is omitted in FIG. 13) of theN-channel SLEDMOS transistor through a first contact hole 56 formed ininterlayer insulating film 55, on the first layer wiring 57, a secondlayer wiring 59 is formed through a second contact hole 58, and on thesecond layer wiring 59, a third layer wiring 61 is formed through a viahole 60.

[0084] Then, a gold bump electrode 63 is formed at a pad portion formedby opening a passivation film 62 on the third layer wiring 61 extendedto separated region from the region forming the via hole 60.

[0085] At this time, the above-mentioned third layer wring 61 is formedwidely because of being a power source line, and it is need to open widecontact hole for the purpose of reduction of contact resistance atcontact-connection with such the wide wiring 61. However, in the case ofconstitution of various kinds of transistors with michronization processsuch as 0.35 μm and the like, opening diameter of the pad portionconstitutes plural fine via holes because the minimum dimension isapplied for dimension of each via hole (contact hole). Because of that,difference in surface of the gold bump electrode 18 remains by havingthe plural fine via holes 15 under the gold bump electrode 18 as thebackground art (FIG. 15).

[0086] Then, the invention forms via holes 60 at separated region fromthe gold bump electrode 63 without forming the via holes 60 under thegold bump electrode 63 formed at the pad portion, so that difference inthe surface of the via holes does not influence surface of the gold bumpelectrode like background art. Therefore, decrease of yield at mountingon TAB and the like caused by difference in the surface of the gold bumpelectrode 63 can be depressed.

[0087] That is, in the case of structure of each transistor constitutingthe display driver with 0.35 μm process such as the embodiment, openingdiameter of the pad portion is constituted by plural fine via holes 15because the minimum dimension is applied for dimension of each via hole(contact hole). Because of that, smoothing of surface of the bumpelectrode is possible by not forming the via holes under the bumpelectrode at michronization process according to the invention.

[0088] Further, by forming the lower layer wiring (the second layerwiring 59, or the second layer wiring 59 and the first layer wiring 57)even at region under the pad not contacting to the upper layer wiring(the third layer wiring 61), difference in face caused by not formingthe lower layer wiring at periphery of the pad portion does not appearthus smooth not damaged.

[0089] Although an example applying the semiconductor device havingthree-layers wiring structure is introduced in the embodiment, theinvention may be applied to a semiconductor device of furthermulti-layers structure.

[0090] Further, although the invention is described about the driver forliquid crystal or EL, the invention is also applicable to various flatpanel display drivers such as an LED display, PDP (Plasma DisplayPanel), FED (Field Emission Display) and so on.

[0091] According to the first aspect of the invention, reduction ofcontact resistance is designed by increasing number of the contactportions so as to decrease on-resistance of the transistor.

[0092] In the device of the invention having various kinds oftransistors and forming contact hole with the minimum dimension indesign rule, reduction of contact resistance is designed by increasingnumber of the contact portions so as to decrease on-resistance of thetransistor by setting suitable number of contacts in every transistorand arranging.

[0093] Making further low resistance is designed by applying for acontact portion for connecting lower layer wiring and upper layer wiringwithout limiting to the contact portion for connecting to thesource/drain layer.

[0094] According to the second aspect of the invention, smooth ofsurface of the bump electrode is designed because the via hole is notformed under the bump electrode formed at the pad portion.

[0095] Smooth of periphery of the pad portion is not damaged by formingthe lower layer wiring at region under the pad portion not contactingthe upper layer wiring.

What is claimed is:
 1. A semiconductor device comprising: a transistoron a semiconductor substrate; and contact portions for connecting alower layer and an upper layer arranged in plural lines.
 2. Asemiconductor device comprising: a first transistor on a semiconductorsubstrate; first contact portions for connecting a lower layer and anupper layer in the first transistor; a second transistor on thesemiconductor substrate; and second contact portions for connecting alower layer and an upper layer in the second transistor, wherein numbersof the first contact portions and the second contact portions aredifferent.
 3. The semiconductor device according to claim 2, wherein thefirst contact portions are arranged in one line, and the second contactportions are arranged in plural lines.
 4. The semiconductor deviceaccording to claim 2, wherein the second transistor further comprises: asource/drain region formed to be adjacent to a gate electrode; and asemiconductor region constituting a channel formed under the gateelectrode.
 5. The semiconductor device according to claim 4, wherein thesecond transistor further comprises a low concentration region of thesame conductive type as the conductive type of the source/drain region,formed to connect to the source/drain region and to contact thesemiconductor region under the gate electrode of the second transistor.6. The semiconductor device according to claim 4, wherein the secondtransistor further comprises a low concentration region of the sameconductive type as the conductive type of the source/drain region,formed being extended shallowly to the semiconductor region to connectto the source/drain region and to contact the semiconductor region underthe gate electrode of the second transistor.
 7. The semiconductor deviceaccording to claim 1, wherein the contact portions are provided forconnecting to the source/drain region.
 8. The semiconductor deviceaccording to claim 1, wherein the contact portions are provided forconnecting to the lower layer wiring and the upper layer wiring.
 9. Thesemiconductor device according to claim 1, wherein a conductive film isburied in the contact portions.
 10. A semiconductor device comprising: alow concentration opposite conductive type source/drain region formed inone conductive type semiconductor; a high concentration oppositeconductive type source/drain region formed in the low concentrationopposite conductive type source/drain region; a gate electrode formed onthe semiconductor through gate oxide film; a one conductive typesemiconductor region formed under the gate electrode and constituting achannel placed between the source/drain region; contact portionscontacting arranged in plural lines; and a source/drain electrodeconnected to the source/drain region through the contact portions.
 11. Amethod of manufacturing a semiconductor device including transistors ona semiconductor substrate, the method comprising a step of formingcontact portions for connecting a lower layer and an upper layer inplural lines.
 12. A method of manufacturing a semiconductor deviceincluding a first transistor and a second transistor on a semiconductorsubstrate, the method comprising the steps of: forming first contactportions for connecting a lower layer and an upper layer in the firsttransistor; forming second contact portions for connecting a lower layerand an upper layer in the second transistor, wherein numbers of thefirst contact portions and the second contact portions are different.13. The method of manufacturing a semiconductor device according toclaim 12, wherein the first contact portions are arranged in one line,and the second contact portions are arranged in plural lines.
 14. Themethod of manufacturing a semiconductor device according to claim 11,wherein the contact portions are provided for connecting to thesource/drain region.
 15. The method of manufacturing a semiconductordevice according to claim 11, wherein the contact portions are providedfor connecting to the lower layer wiring and the upper layer wiring. 16.A method of manufacturing a semiconductor device including a gateelectrode on a one conductive type semiconductor through gate oxidefilm, the method comprising the steps of: forming a low concentrationopposite conductive type source/drain region by ion-implanting oppositeconductive type impurity in the semiconductor; forming a lowconcentration opposite conductive type region connecting to the lowconcentration opposite conductive type source/drain region byion-implanting opposite conductive type impurity; forming a highconcentration opposite conductive type source/drain region in the lowconcentration opposite conductive type source/drain region byion-implanting opposite conductive type impurity; forming a oneconductive type body region dividing the opposite conductive type regionunder the gate electrode by ion-implanting one conductive type impurity;and forming contact portions for connecting to the source/drain regionin plural lines through an interlayer insulating film covering the gateelectrode.
 17. The method of manufacturing a semiconductor deviceaccording to claim 11, further comprising a step of burying a conductivefilm in the contact portions.
 18. A semiconductor device not forming anyvia hole under a bump electrode provided at a pad portion.
 19. Asemiconductor device comprising: an upper layer wiring; a lower layerwiring; a via hole connecting the upper layer wiring and the lower layerwiring; and a bump electrode provided at a pad portion covering lowerlayer wiring, wherein the via hole is formed at a region except underthe bump electrode.
 20. The semiconductor device according to claim 18,wherein further comprising a lower layer wiring arranged under the bumpelectrode.
 21. A semiconductor device comprising: a gate electrodeformed on a semiconductor substrate through gate oxide film; asource/drain region formed so as to be adjacent to the gate electrode; asemiconductor region formed under the gate electrode and constituting achannel; a lower layer wiring connected to the source/drain region withcontact; a via hole formed in an interlayer insulating film covering thelower layer wiring and formed at a region except a bump electrodeprovided at a pad portion; and an upper layer wiring connected to thelower layer wiring with contact through the via hole.
 22. Thesemiconductor device according to claim 21, further comprising a lowconcentration region of the same conductivity type as the source/drainregion formed under the gate electrode so as to connect to thesource/drain region and to contact the semiconductor region.
 23. Asemiconductor device according to claim 21, further comprising a lowconcentration region of the same conductivity type as the source/drainregion formed extending shallowly to surface layer of the semiconductorunder the gate electrode so as to connect to the source/drain region andto contact the semiconductor region.
 24. A method of manufacturing asemiconductor device not forming a via hole under a bump electrodeconstituted at a pad portion.
 25. A method of manufacturing asemiconductor device connecting to an upper layer wiring with contactthrough a via hole formed interlayer insulating film covering a lowerlayer wiring, the method comprising the steps of: forming in theinterlayer insulating film so as to cover the lower layer wiring;forming the upper layer wiring so as to contact the lower layer wiringthrough the via hole after forming the via hole at region except a padforming portion of the interlayer insulating film; and forming a bumpelectrode at a pad portion.
 26. The method of manufacturing asemiconductor device according to claim 24, forming a lower layer wiringunder the bump electrode.
 27. A method of manufacturing a semiconductordevice including a gate electrode on a one conductive type semiconductorthrough gate oxide film, the method comprising the steps of: forming alow concentration opposite conductive type source/drain region byion-implanting opposite conductive type impurity in the semiconductor;forming a low concentration opposite conductive type region connectingto the low concentration opposite conductive type source/drain region byion-implanting opposite conductive type impurity; forming a highconcentration opposite conductive type source/drain region in the lowconcentration opposite conductive type source/drain region byion-implanting opposite conductive type impurity; forming a oneconductive type body region dividing the opposite conductive type regionunder the gate electrode by ion-implanting one conductive type impurity;forming a lower layer wiring connecting to the source/drain region withcontact through interlayer insulating film covering the gate electrode;forming a via hole at a region except a bump electrode provided at a padportion of the interlayer insulating film after forming the interlayerinsulating film to cover the lower layer wiring; and forming an upperlayer wiring connected to the lower layer wiring through the via hole.